The performance of a p-type field-effect transistor (PFET) in a semiconductor device depends on a variety of factors. One factor is the contact resistance between the silicide contacts and the source/drain regions of the underlying silicon layer. The lower the resistance, the higher the performance of the PFET. Likewise, the greater the resistance, the lower the performance of the PFET.
In conventional semiconductor devices, to reduce the contact resistance between the silicide contacts and the source/drain regions, a boron-doped silicon-germanium layer would be embedded in the silicon layer, and the silicide contacts would be disposed on the boron-doped silicon-germanium layer. The boron-doped silicon-germanium layer had to be formed prior to source/drain anneal. Because source/drain anneal causes boron ions to migrate away from the silicon-germanium and into the surrounding silicon, the silicon-germanium layer would be doped with an amount of extra boron ions calculated to result in the correct doping post-anneal.
Moreover, the embedded silicon-germanium layer generally prevents the use of a very thin substrate, such as a thin upper silicon layer that is part of a silicon-on-insulator (SOI) wafer.